(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the degradation of thin gate oxides caused by plasma processing of polysilicon gate field effect transistors.
(2) Description of Prior Art and Background to the Invention
In the manufacture of high density integrated circuits using polysilicon gate MOSFETs (metal oxide silicon field effect transistors) technology, the oxide layer which forms the gate insulation of the MOSFET is extremely thin, in many cases, less than 100 Angstroms. When the surface of a polysilicon gate electrode or any metal layer connected to the polysilicon gate metal is subjected to plasma processing, such as in the formation of insulative sidewalls used in the LDD (lightly doped drain) structure, charges from the plasma accumulate on the metal surface. The exposed metal surface acts as an antenna, accumulating charge from the plasma and thereby developing a high electrical potential across the gate oxide. Initial exposure occurs during the patterning of the polysilicon gate electrodes. The nature of the charging varies across the wafer, being either positive or negative depending on the balance of ion and electron fluxes in the plasma. Non-uniform plasmas such as those influenced by magnetic fields can produce a high electron flux near the periphery of the wafer and high positive ion flux near the center (Wolf, S., "Silicon Processing for the VLSI Era", Vol.3, Lattice Press, Sunset Beach, Calif., (1995), p507).
After a gate oxide layer is formed on a silicon wafer substrate, the layer is covered with a layer of polysilicon or polycide within which a gate electrode is defined. The polysilicon layer is then anisotropically etched by a plasma process to form the gate electrode. This is the first in a series of plasma exposures of the gate conductive path. In this instance the area of the gate electrode is covered with photoresist and only edge regions are exposed to the plasma. After the gate electrode is formed LDD (lightly doped drain) regions are formed in the silicon active area adjacent to the gate electrode by ion implantation. A layer of insulative material such as silicon oxide is then conformally deposited over the wafer. This layer is then anisotropically etched back to re-expose the polysilicon gate and gate oxide, leaving an insulative sidewall along the periphery of the polysilicon structures. This time the entire surface of the polysilicon gate electrode is exposed to the plasma at end point and during a brief over-etch period.
Krishnan, et.al. U.S. Pat. No. 5,739,052 cites a method and test device for evaluating plasma gouging of oxide at the periphery of a polysilicon gate electrode by the polysilicon gate etching process. After etching the gate element, a blanket polysilicon layer is deposited and anisotropically etched to form a sidewall which now encompasses the gouged portion of the oxide and creates a second gouged region at the periphery of the sidewall. Oxide breakdown measurements are used to assess the gouging damage. Shiue, et.al., U.S. Pat. No. 5,781,445 shows a plasma damage FET test device, formed on a product wafer, for charging damage caused by plasma processing of upper level metallization. A conductive cover is formed over the device at a selected metallization level to shields the device from damage during subsequent plasma processing. By forming device shielding at different metallization levels, shifts in threshold voltages of the various devices isolate the processing steps in which plasma damage is incurred. Chen, et.al., U.S. Pat. No. 5,646,074 cites the use of Q.sub.BD and E.sub.BD measurements to evaluate gate oxide deterioration incurred during a chemical cleaning step for removing photoresist. Alers, et.al., U.S. Pat. No. 5,804,795 describes a method of detection and characterizing of oxide breakdown by the measurement of the intensity of noise signals emitted as breakdown processes occur. Hause, et.al., U.S. Pat. No. 5,759,871 cites a junction leakage monitor structure.
Progress has been made in the design of plasma etching tools to reduce the bombardment of substrate surfaces by excessive and unbalance charge flux from the plasma and thereby reduce the susceptibility of sensitive device regions to current degradation. However, in the new HDP (high density plasma) reactor designs, electron shading is believed to be the predominant charging mechanism which causes degradation of thin gate oxides. Electron shading occurs in plasmas as a result of the difference in isotropy between electrons and positive ions crossing the plasma sheath and onto the wafer surface. Because electrons and ions interact differently with closely spaced structures on the wafer surface, a differential charging occurs between the structures. Such a charging effect would lead to the development of a positive charge on the polysilicon gate during LDD sidewall etching.
The mechanism of current flow through gate oxides less than 100 Angstroms thick is primarily Fowler-Nordheim(FN) tunneling. FN tunneling occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electrode potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 Angstroms. Such potentials are readily achieved during charging in conventional plasma reactors. Excessive FN tunneling currents eventually lead to positively charged interface traps in the oxide which may lead to subsequent dielectric breakdown. Thus plasma exposure may not only lower the breakdown voltage thresholds but can also sufficiently degrade the oxide to create reliability concerns.
Recent improvements in plasma tool design have greatly reduced gate oxide damage by charging. However, factors other than tool design also contribute to plasma induced damage. The components of the etch gases themselves can influence the degree of oxide damage. Familiar etchant gases such as SF.sub.6, which are highly electronegative, are also prone to induce a higher degree of plasma damage in thin gate oxides than other gas components. Again, by careful selection of gas composition and etchant parameters it is possible to further reduce plasma damage from a particular etch process. Once the process is optimized it would be expected that the gate oxide damage would be minimal and controllable in a manufacturing process.
However, in practice, this is not the case. Modern plasma etching tools are very complex and expensive and are called upon to perform a variety of etching tasks at various stages of integrated circuit manufacturing. The great variety of etching steps, involving different etchant gases, parameters, and materials to be etched do not permit the dedication of a single etching tool to each process step. Therefore, plasma etching machines are also designed to accommodate a large variety of etching tasks involving different etchant chemistries and conditions.
It has been observed by the present researchers that, when a commercial plasma etcher is used for multiple etching tasks involving a variety of different types of manufactured product, the amount of plasma damage incurred also depends upon the process history of the etching tool. For example, the damage incurred in the tunneling oxide of an EEPROM integrated circuit product during spacer etching is markedly greater than normal when the spacer etch job has been preceded by a via etch of a BiCMOS product. The influence of the BiCMOS via job in degrading thin oxide quality may persist in the etching tool over several successive jobs before the chamber recovers to a suitable level. This influence of preceding jobs in a plasma tool on the outcome of a current job is referred to herein as the chamber history effect. While chamber history is of limited consequence to the outcome of many plasma etching operations such as via etching, it is of particular importance to gate LDD sidewall etchback in the manufacture of self-aligned gate MOSFETs and in the formation of sidewall oxide over tunnel oxide layers in the manufacture of EEPROMS. It is therefore desirable to have a means for quickly, easily, and routinely qualifying a plasma etching tool prior to damage sensitive jobs such as those involving exposure to plasmas of device components adjoined to thin gate or tunnel oxides.